Patent · US Active

CMOS devices and fabrication method

US8901675B2 · kind B2 · utility

1Cited by
0References
20Claims
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Assignee

Inventors

Key dates

Filing dateDec 14, 2012
Grant dateDec 2, 2014
Priority date
Expiry dateDec 14, 2032

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/83135

Abstract

A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.