Semiconductor package with embedded die and its methods of fabrication
US8901724B2 · kind B2 · utility
20Cited by
65References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Jul 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0152
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.