Semiconductor chip layout
US8901747B2 · kind B2 · utility
15Cited by
31References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2010 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | May 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip layout for a high speed semiconductor device is disclosed. The chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. A serial interface is centrally located to reduce latency, power and propagation delays. Stacked die that contain one or more devices with the chip layout are characterized by having improved latency, bandwidth, power consumption, and propagation delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.