Method and circuit for suppressing bias current and reducing power loss
US8902614B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2009 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, the current suppression circuit applies a voltage to the node in response to a heavy load. In another operating mode, the current suppression circuit lowers the voltage at the node in response to a light load or no load. Lowering the voltage at the node decreases the flow of bias current through the circuit element thereby lowering power loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.