Patent · US Active

Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

US8903882B2 · kind B2 · utility

2Cited by
3References
13Claims
0Family size

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Inventors

Key dates

Filing dateJul 15, 2011
Grant dateDec 2, 2014
Priority date
Expiry dateJul 4, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2207/3828
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.