Philipp Panitz
14Patents
2h-index
14Co-inventors
43Inventor score
Filing activity: Jul 1, 2008 → Jan 8, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9207995B2 | Mechanism to speed-up multithreaded execution by register file write port reallocation | Physics | 27 | Active |
| US8015527B2 | Routing of wires of an electronic circuit | Physics | 4 | Active |
| US8903882B2 | Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product | Physics | 2 | Active |
| US8407654B2 | Glitch power reduction | Physics | 2 | Active |
| US8972961B2 | Instruction scheduling approach to improve processor performance | Physics | 1 | Active |
| US8612911B2 | Estimating power consumption of an electronic circuit | Physics | 1 | Active |
| US8935685B2 | Instruction scheduling approach to improve processor performance | Physics | 1 | Active |
| US9164725B2 | Apparatus and method for calculating an SHA-2 hash function in a general purpose processor | Electricity | 1 | Active |
| US8627263B2 | Gate configuration determination and selection from standard cell library | Physics | 0 | Active |
| US9256430B2 | Instruction scheduling approach to improve processor performance | Physics | 0 | Active |
| US8731858B2 | Method and system for calculating timing delay in a repeater network in an electronic circuit | Physics | 0 | Active |
| US8959275B2 | Byte selection and steering logic for combined byte shift and byte permute vector unit | Electricity | 0 | Active |
| US9043673B2 | Techniques for reusing components of a logical operations functional block as an error correction code correction unit | Electricity | 0 | Active |
| US8959276B2 | Byte selection and steering logic for combined byte shift and byte permute vector unit | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.