High speed serial peripheral interface system
US8904078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.