Transistor having impurity distribution controlled substrate and method of manufacturing the same
US8907406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Jan 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device according to embodiments includes a semiconductor substrate, a buried insulating layer which is formed on the semiconductor substrate, a semiconductor layer which is formed on the buried insulating layer and includes a narrow portion and two wide portions which are larger than the narrow portion in width and are respectively connected to one end and the other end of the narrow portion, a gate insulating film which is formed on a side surface of the narrow portion, and a gate electrode formed on the gate insulating film. The impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the narrow portion, and the impurity concentration of the semiconductor substrate directly below the narrow portion is higher than the impurity concentration of the semiconductor substrate directly below the wide portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.