Delay difference detection and adjustment device and method
US8907709B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2014 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Jun 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a delay difference detection and adjustment device comprising: a first delay circuit including first delay units to receive and transmit a first clock; a second delay circuit including second delay units to receive and transmit a second clock; a storage circuit including storage units, each of which includes a data input end to receive the first clock and an operation clock reception end to receive the second clock, so that the storage circuit is operable to save a plurality of levels of the first clock according to the second clock; a delay control circuit to adjust the delay amount of the second delay circuit; and an analyzing circuit to generate an analysis result according to the cycle and levels of the first clock in which the analysis result indicates or is used to derive a unit delay difference between the first and second delay units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.