Content addressable memory (“CAM”)
US8908407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory device based on an extremely compact design, potentially as small as 16F2 per memory cell. One embodiment is based on cells having two memory storage elements, such as RRAM elements. Each RRAM element and a respective FET are connected in series between a common matchline and a respective bitline. Cell content for each cell is matched against a bit of a search word by applying voltages to the respective bitlines dependent upon bit value and causing one of the two RRAM elements for each cell to discharge the matchline over a low resistance path in event of mismatch between the cell content and the bit. If no “quick” discharge occurs for multiple cells of a row, then a match is detected. In addition, a matchline recharge path to a high voltage bitline is substantially eliminated by controlling the FETs with specific wordline voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.