Inter-integrated circuit (I2C) multiplexer switching as a function of clock frequency
US8909844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2012 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Feb 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.