Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction
US8909908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2009 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Apr 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.