Patent · US Active

Recoverable parity and residue error

US8909988B2 · kind B2 · utility

2Cited by

3References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zeev Sperber · Jerusalem, IL
Ofer Levy · Atlit, IL
Michael Mishaeli · Jerusalem, IL
Ron Gabor · Raanana, IL

Key dates

Filing date	Mar 30, 2012
Grant date	Dec 9, 2014
Priority date	—
Expiry date	Feb 9, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1032
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.