Model based simulation method with fast bias contour for lithography process check
US8910092B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2013 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Integrated circuit design techniques are disclosed. In some methods, a target layout design having a geometric pattern thereon is received. A set of fast-bias contour (FBC) rules is applied to the target layout design to provide an electronic photomask having FBC-edits. The FBC-edits differentiate the electronic photomask from the target layout design, and the FBC rules are applied without previously applying optical proximity correction (OPC) to the target layout design. A lithography process check is performed on the electronic photomask to determine whether a patterned integrated circuit layer, which is to be manufactured based on the electronic photomask, is expected to be in conformance with the geometric pattern of the target layout design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.