Method for manufacturing MOS transistors with different types of gate stacks
US8912067B2 · kind B2 · utility
2Cited by
0References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2011 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Sep 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.