Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimization
US8912104B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2011 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Dec 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.