Method and apparatus for using a synchronous reset pulse to reset circuitry in multiple clock domains
US8912829B1 · kind B1 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2013 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Aug 12, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.