Triple-damascene interposer
US8913402B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2011 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Feb 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This interposer provides interconnections between stacked layers of circuits, which may include integrated circuits, PC boards, and hybrid substrates. Fabricated as an integrated circuit itself using readily available process steps, this interposer uses single and dual-damascene layers to increase the density of usable interconnections on both its top and bottom surfaces. Access from a top surface to a bottom surface is provided by conductive through-vias that may be placed at a high density. For even greater density, interconnections may be routed within silicon trenches, while damascene processing reduces the total number of steps required for fabrication. The described techniques may be used to create double-sided integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.