Patent · US Active

Dual clock edge triggered memory

US8913457B2 · kind B2 · utility

1Cited by

7References

26Claims

0Family size

Assignees

STMicroelectronics International N.V. · NL
STMicroelectronics SA

Inventors

Nishu Kohli · Kunzer, IN
Robin Wilson · Holywood, GB

Key dates

Filing date	May 6, 2014
Grant date	Dec 16, 2014
Priority date	—
Expiry date	May 6, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/222
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.