Hierarchical error correction
US8914712B2 · kind B2 · utility
3Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2012 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Aug 25, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data processing device can perform error detection and correction in two stages: in the first stage, error detection is performed for the load data using the in-line error detection information. If a first type of error is detected in the data segment, the error is corrected using the in-line error detection information. If a second type of error is detected error correction is performed using the residual sum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.