Method of manufacturing sidewall spacers on a memory device
US8916470B1 · kind B1 · utility
0Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Oct 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.