Vertical tunnel field effect transistor (FET)
US8916927B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2012 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Sep 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/517
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.