LDMOS semiconductor device with parasitic bipolar transistor for reduced surge current

US8916931B2 · kind B2 · utility

Assignee

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

• Yasuhiro Takeda · Kodaira, JP
• Seiji Otake · Saitama, JP

Key dates

• Filing date: Nov 1, 2011
• Grant date: Dec 23, 2014
• Expiry date: Feb 2, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/393

Abstract

An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.