Semiconductor package including multiple chips and memory system having the same
US8917110B2 · kind B2 · utility
6Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2012 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Sep 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A package includes a master chip including a storage circuit configured to store an impedance setting of the master chip and an impedance setting of a slave chip, and a termination circuit for an impedance matching with an outside of the package, and the slave chip connected to the master chip, wherein if a termination operation for the slave chip is activated, the termination circuit of the master chip performs an impedance matching operation using the impedance setting for the slave chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.