Path isolation in a memory device
US8917534B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 2011 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Sep 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one embodiment, a memory device includes a memory cell of a memory device, a bit-line coupled to the memory cell, a word-line coupled to the memory cell, a bit-line electrode coupled to the bit-line, a word-line electrode coupled to the word-line, current-limiting circuitry of a selection module coupled to one of the word-line electrode and the bit-line electrode having a lower potential, the current-limiting circuitry to facilitate a selection operation of the memory cell by the selection module, sensing circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the sensing circuitry to perform a read operation of the memory cell, and write circuitry coupled to the one of the word-line electrode and the bit-line electrode having the lower potential, the write circuitry to perform a write operation of the memory cell. Other embodiments may be described and/or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.