Input/output (I/O) expansion response processing in a peripheral component interconnect express (PCIe) environment
US8918573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2010 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Dec 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to optimizing EDRAM refresh rates in a high performance cache architecture. A request is received from a requester to perform an operation on an I/O adapters. It is determined if the request is in a format other than a format supported by an I/O bus and if, the requester requires a completion response for the request. The request is transformed into the format supported by the I/O bus and is transmitted to the I/O adapter. The completion response is received from the I/O adapter, and includes an indicator that the request has been completed. The completion response is in the format supported by the I/O bus and is transmitted to the requester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.