Multi-interface memory with access control
US8918594B2 · kind B2 · utility
4Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2010 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Jun 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods disclose techniques to control access to a memory array. The memory array can be accessed by either a first interface or a second interface. A switch register grants privilege levels, which control access. For example, a high privilege level can grant access and a low privilege level can deny access. A status register indicates when an interface with a high privilege level is busy accessing the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.