Speculative scheduling of memory instructions in out-of-order processor based on addressing mode comparison
US8918625B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2011 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Feb 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor that executes instructions out of program order is described. In some implementations, a processor detects whether a second memory operation is dependent on a first memory operation prior to memory address calculation. If the processor detects that the second memory operation is not dependent on the first memory operation, the processor is configured to allow the second memory operation to be scheduled. If the processor detects that the second memory operation is dependent on the first memory operation, the processor is configured to prevent the second memory operation from being scheduled until the first memory operation has been scheduled to reduce the likelihood of having to reexecute the second memory operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.