Methods for controlling wafer curvature
US8918988B2 · kind B2 · utility
1Cited by
12References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Nov 23, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49167
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and structures for controlling wafer curvature during fabrication of integrated circuits caused by stressed films. The methods include controlling the conductor density of wiring levels, adding compensating stressed film layers and disturbing the continuity of stress films with the immediately lower layer. The structure includes integrated circuits having compensating stressed film layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.