Semiconductor integrated device assembly process
US8921164B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 20, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Mar 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83385
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.