Edge and strap cell design for SRAM array
US8921179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Mar 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.