Semiconductor device and method of forming high voltage SOI lateral double diffused MOSFET with shallow trench insulator
US8921186B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2009 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Dec 31, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The drift region has a graded doping distribution. A co-implant region is formed in the active silicon. A source region is formed in the co-implant region. A shallow trench insulator is formed along a top surface of the LDD drift region. The shallow trench isolator has a length less than the LDD drift region. The shallow trench insulator terminates under the polysilicon gate and within the LDD drift region. A polysilicon gate is formed above the active silicon layer between the source region and LDD drift region and at least partially overlapping the shallow trench insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.