Stacked wafer with coolant channels
US8921992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer assembly with internal fluid channels. The assembly is fabricated by creating one or more channels in a first surface of a first semiconductor wafer and creating an oxide surface on the first surface of the first semiconductor wafer. An oxide surface is also created on a first surface of a second semiconductor wafer. The assembly is fabricated by bonding the oxide surface of the first surface of the first semiconductor wafer to the oxide surface of the first surface of the second semiconductor wafer to create a wafer assembly and to seal the one or more channels at edges defined by the bonded first and second surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.