Cell balance configuration for pin count reduction
US8922165B2 · kind B2 · utility
10Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 14, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jun 19, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02T10/70
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments of an electronic circuit for monitoring a battery stack enable cell balancing while conserving pin-count of the circuit package. The illustrative electronic circuit comprises a battery monitoring integrated circuit configured for monitoring a plurality of cells in the battery stack. The battery monitoring integrated circuit is arranged to share a common node pin between two adjacent battery cells in the battery stack for the purpose of cell balancing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.