Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs)
US8922415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Aug 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/462
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.