Method of identifying damaged bitline address in non-volatile
US8923083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Mar 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.