Method and apparatus for low jitter distributed clock calibration
US8924765B2 · kind B2 · utility
1Cited by
12References
31Claims
0Family size
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Inventor
Key dates
| Filing date | Feb 21, 2012 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jan 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/50
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.