Constructing equivalent waveform models for static timing analysis of integrated circuit designs
US8924905B1 · kind B1 · utility
9Cited by
3References
17Claims
0Family size
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Key dates
| Filing date | Jun 21, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Jun 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.