High threshold voltage NMOS transistors for low power IC technology

US8927361B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Roger A. Booth, Jr. · Wappingers Falls, US
• Victor Chan · Guilderland, US
• Narasimhulu Kanike · Wayne, US
• Huiling Shang · Bethlehem, US
• Varadarajan Vidya · Wappingers Falls, US
• Jun Yuan · San Diego, US

Key dates

• Filing date: Mar 13, 2013
• Grant date: Jan 6, 2015
• Expiry date: Apr 14, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.