Nitride semiconductor wafer including different lattice constants
US8928000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Mar 14, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/01335
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×1018 cm−3 or more and less than 1×1021 cm−3. The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.