Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package
US8928132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2011 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Sep 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package having a reduced size by including an interposer having through substrate vias (TSVs), the semiconductor package may comprise a lower semiconductor package which includes a lower base substrate, an interposer with TSVs on the lower base substrate, and a lower semiconductor chip on the interposer and electrically connected to the interposer. The semiconductor package may include an upper semiconductor package on the lower semiconductor package including an upper semiconductor chip and package connecting members on the interposer and electrically connect the upper semiconductor package to the interposer. An exterior molding member may be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.