Semiconductor memory device and method of operating the same
US8929155B2 · kind B2 · utility
1Cited by
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10Claims
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Key dates
| Filing date | Jul 15, 2011 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | May 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes memory cells for storing data, page buffers each configured to comprise a dynamic latch and a static latch on which data to be programmed in to the memory cells or data read from the memory cells are latched, and a control logic configured to store a plurality of refresh mode select codes corresponding to various refresh cycles, and refresh the dynamic latch by exchanging data between the static latch and the dynamic latch according to a refresh cycle corresponding to a selected refresh mode select code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.