Method and apparatus for synchronization of data and error samples in a communications system
US8929501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Sep 15, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0038
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.