Smart memory
US8930618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2011 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Aug 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a storage device comprising a plurality of memory tiles each comprising a memory block and a processing element, and an interconnection network coupled to the storage device and configured to interconnect the memory tiles, wherein the processing elements are configured to perform at least one packet processing feature, and wherein the interconnection network is configured to promote communication between the memory tiles. Also disclosed is a network component comprising a receiver configured to receive network data, a logic unit configured to convert the network data for suitable deterministic memory caching and processing, a serial input/output (I/O) interface configured to forward the converted network data in a serialized manner, a memory comprising a plurality of memory tiles configured to store and process the converted network data from the serial I/O interface, and a transmitter configured to forward the processed network data from the serial I/O interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.