Arrangement
US8930637B2 · kind B2 · utility
0Cited by
7References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Aug 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1663
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An arrangement includes a first part and a second part. The first part includes a memory controller for accessing a memory, at least one first cache memory and a first directory. The second part includes at least one second cache memory configured to request access to said memory. The first directory is configured to use a first coherency protocol for the at least one first cache memory and a second different coherency protocol for the at least one second memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.