Method and apparatus for supporting target-side security in a cache coherent system
US8930638B2 · kind B2 · utility
3Cited by
1References
29Claims
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Key dates
| Filing date | Nov 27, 2012 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | May 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.