Logical address offset in response to detecting a memory formatting operation
US8930671B2 · kind B2 · utility
1Cited by
13References
20Claims
0Family size
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Key dates
| Filing date | Feb 20, 2014 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.