Method of sharing and re-using timing models in a chip across multiple voltage domains

US8930864B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Debjit Sinha · Wappingers Falls, US
• Eric Jason Fluhr · Round Rock, US
• Stephen G. Shuma · Underhill, US
• Natesan Venkateswaran · Hopewell Junction, US
• Chandramouli Visweswariah · Croton-on-Hudson, US
• Michael H. Wood · Detroit, US
• Vladimir Zolotov · Putnam Valley, US

Key dates

• Filing date: Oct 3, 2012
• Grant date: Jan 6, 2015
• Expiry date: Oct 3, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.