Patent · US Active

Optimized buffer placement based on timing and capacitance assertions

US8930870B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Lukas Daellenbach · Altdorf, DE
Elmar Gaugler · Eppelheim, DE
Ralf Richter · Dresden, DE

Key dates

Filing date	Sep 24, 2013
Grant date	Jan 6, 2015
Priority date	—
Expiry date	Sep 24, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Optimized buffer placement is provided based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. An estimated slack is calculated for each branch, the branches are arranged according to the calculated slack, decoupling buffers are inserted in all branches except the most critical branch(es), the most critical branch(es) are globally routed and slew conditions are fixed within this branch, and at least one next branch is globally routed and slew conditions are fixed therein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.