Patent · US Active

Creating regional routing blockages in integrated circuit design

US8930873B1 · kind B1 · utility

2Cited by

12References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Charles J. Alpert · Cedar Park, US
Zhuo Li · Austin, US
Gi-Joon Nam · Austin, US
Sven Peyer · Lörrach, DE
Sourav Saha · Sherghati, IN
Chin Ngai Sze · Austin, US
Yaoguang Wei · Austin, US

Key dates

Filing date	Nov 15, 2013
Grant date	Jan 6, 2015
Priority date	—
Expiry date	Nov 15, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/394
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A region of congestion is detected at a set of layers. The region occupies the same area of each layer in the set. A routing blockage is defined as a tuple corresponding to the region. The tuple includes a set of coordinates to describe an area of the region, a first and a second layer coordinates of a first and a second layer in the set of layers. The routing blockage is applied during an iteration of rough routing. Before an iteration of detailed routing, the routing blockage is removed. Detailed routing is performed using a g-cell in the region. The detailed routing uses a routing capacity saved in the g-cell during the iteration of rough routing due to the routing blockage. A revised IC design is produced where a revised congestion in an area corresponding to the region is reduced.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.